1. Field of the Invention
The present invention is related to an Analog to Digital Converters (ADC), and particularly, related to an ADC which can save power consumption and occupy a small chip area.
2. Description of the Prior Art
Analog to Digital Converters (ADC) convert analog signals of the real world into digital data, so the digital data can be processed by Digital Signal Processors (DSP). As the information technology gets populated, many products include various types of multimedia functions; for example, the processing of the image and voice signals includes using ADC to convert the analog signals into the digital format, and the digital data is sent to DSP for further processing; finally, the processed result can be delivered to the output device, the network or some digital storage device. On the other hand, various types of sensors have been used; for example, a digital thermometer is using a temperature sensor to generate analog temperature signals, which are then converted into digital format by an ADC. The digital data can be then be processed, calibrated and displayed by the thermometer. For a broader view, especially in the medical, communication and control domains, the ADCs are getting more popular and almost can be found everywhere. Among them, a Successive Approximation Analog to Digital Converter (SAR ADC) is a special type of ADC, and is mostly utilized in the moderate- or low-speed (of data rate) applications.
Please refer to FIG. 1, which illustrates a schematic diagram of a Successive Approximation Analog to Digital Converter (SAR ADC) 10. The SAR ADC 10 comprises a sample and hold circuit 100, a comparator 102, a successive control unit 104 and a digital to analog converter (DAC) 106. The operations of the ADC 10 can be stated as follows. Firstly, the sample and hold circuit 100 samples an input signal VIN and outputs a sampled voltage VSIN. The comparator 102 compares the voltage level of the sampled voltage with an analog voltage VCOM, and the comparing result is outputted to the successive control unit 104. The successive control unit 104 will generate a digital data DK according to the comparing result produced by the comparator 102. The digital to analog converter 106 converts the digital data DK into an analog voltage VCOM, and output to the comparator 102.
Inside the ADC 10, the successive control unit 104 controls a repeating process for generating one more valid (less significant) bit according to the comparing result outputted by the comparator 102. The digital data DK thus includes increasing number of valid bits so that the analog voltage VCOM produced by the DAC 106 can get closer and closer to the sampled voltage VSIN, and the ADC 10 repeats this process till all the valid bits are generated. General speaking, the number of bits is closely related to the precision of the ADC 10, and as the number of valid bits increases, so does the precision as well as the cost of increasing number of the repeating processes.
However, traditional Successive Approximation Analog to Digital Converter (SAR ADC) must include an independent digital to analog converter (DAC) and some technical issues are thus brought up to table. Please refer to FIG. 2, which illustrates a schematic diagram of a 7-bit Charge-Redistribution SAR ADC 20. The ADC 20 comprises a sample and hold circuit 200 (not shown in FIG. 2), a comparator 202, a successive control unit 204, a DAC 206 and a reference voltage output unit 208. The ADC 20 is a special but popular type of the more general ADC 10. The ADC 20 utilizes a special charge redistribution technique to complete the analog-to-digital conversion process. The digital to analog converter 206 of the ADC 20 is formed by switches S0˜S7 and capacitors C1˜C7, and the capacitances of the capacitors C1˜C7 are of specific but different values. Since the terminals of the capacitors C1˜C7 are connected to the same voltage level, the capacitance of the capacitors C1˜C7 will decide how much electric charges are being stored in each of the capacitors C1˜C7. Since the different capacitances of the capacitors C1˜C7 are having definite proportional relationships, such that the charge stored in the capacitors C1˜C7 will also have the same definite proportional relationships; if not, the ADC won't work precisely. Meanwhile and most importantly, the charge vs. applied voltage of each of the capacitors C1˜C7 should be precisely linear, such that the output result of the analog to digital conversion can be precise enough, and the metal-insulator-method capacitor (MIMC) are most qualified to the said requirements. In other words, in today's semiconductor technology, the capacitor using MIMC structure includes a much better linearity than other capacitor structures, including metal-oxide-semiconductor capacitor (MOSC). However, the capacitance per unit area of the MIMC is around 1˜2(fF/m2) and is far less than that of the MOSC, which is around 7(fF/m2). In other words, for forming a capacitor of certain capacitance, the chip area occupied by the MIMC structure will be much more than that by the MOSC structure. However, the linearity of the MOSC is not as good as the MIMC, and is not good to be used under the structure of the ADC 20.
Besides that, both the ADC 10 and the special ADC 20 requires the digital to analog converter 206, which further needs the reference voltage output unit 208 to provide a reference voltage VREF. According to experimental results, the power consumed by the reference voltage output unit 208 almost takes a half of the power consumption of the ADC 20. However, the DAC 206 is an indispensable part of the ADC 20. The large power consumption of the reference voltage output unit 208 results in large power consumption of the ADC 20.